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| 14/10/2005 |
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Презентация нового продукта компании Philips Semiconductors «ARM7 mini - новое семейство микроконтроллеров Philips для экономичных решений»
19 октября 2005 в рамках выставки «ChipEXPO», компания Philips Semiconductors проводит презентацию нового продукта ARM mini
В презентации будут раскрыты следующие вопросы:
• Рынок ARM устройств
• Преимущества архитектуры ARM
• Особенности микроконтроллеров семейства ARM mini: LPC2101/02/03
• Средства разработки, отладки и визуального программирования
• Документация и источники дополнительной информации
Презентация будет проходить:
19 октября, среда
с 15:00 до 16:00
По адресу: г.Москва, выставочный комплекс «Экспоцентр»,
Краснопресненская наб., д. 14.
Зал «Стеклянный купол».
Дополнительную информацию о новом продукте Вы можете найти на сайте, воспользовавшись следующими ссылками:
http://www.semiconductors.philips.com/news/pressreleases/images/1188_hi.jpg
http://www.semiconductors.philips.com/news/content/file_1188.html |
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| 24/05/2004 |
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eNews from Philips Semiconductors
Product of the week
PBLS1503V
15 V BISS Loadswitch in SOT666
http://www.semiconductors.philips.com/pip/PBLS1503V.html
BISS Loadswitches combine a lowVCEsat (BISS) transistor and a resistor-equipped transistor (RET) in a single compact package, dramatically reducing component count and board space requirements. The PBLS1503V is ideal for supply line switches, battery charger switches and high-side switches for LEDs, drivers, backlights and portable equipment.
Top headlines
- Philips showcases multi-view 3-D display technology at SID 2004
http://www.semiconductors.philips.com/news/content/file_1061.html
News articles
New power management MOSFETs
Philips is further expanding its portfolio of TrenchMOSTM devices with the release of the PHP18NQ11T
http://www.semiconductors.com/pip/PHP18NQ11T.html and PHX18NQ11T
http://www.semiconductors.com/pip/PHX18NQ11T.html. Rated at 110 V, they are ideal for demanding applications such as class D audio amplifiers, motor control and DC/DC conversion.
╣TrenchMOS - a new dimension in power
With the release of a new series of highly efficient MOSFETs in the ultra-compact SOT416 (SC-75) package, Philips provides even more power management options for system designers. Part of the ╣TrenchMOS family, the new PMR devices boast extremely low RDS(on) values and are available in 20 V, 30 V and 60 V options. For more details, download our product leaflet
http://www.semiconductors.philips.com/acrobat/literature/9397/75013081.pdf.
New STARplug SMPS controller ICs
The new TEA162x devices are highly efficient controller ICs that enable the creation of compact and environmentally friendly switched mode power supplies (SMPSs). They are manufactured using Philips' high-voltage EZ-HV silicon-on-insulator technology combined with a low-voltage BiCMOS process, and operate from a rectified universal mains supply. The first products in the family are:
- TEA1620P
http://www.semiconductors.philips.com/pip/TEA1620P_N1.html
- TEA1622P
http://www.semiconductors.philips.com/pip/TEA1622P_N1.html
- TEA1623P
http://www.semiconductors.philips.com/pip/TEA1623P_N1.html
An introduction to low-voltage DC motors
This new application note from Philips describes the physical construction and electrical characteristics of typical brushed' and brushless' low-voltage DC motors. It includes a comparison of the relative merits of various power devices and gives detailed guidance on choosing the right power MOSFET for the application. To download the note, click here
http://www.semiconductors.com/acrobat/applicationnotes/AN10293_1.pdf.
New product information
Discretes: Power
PHX45NQ11T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHX45NQ11T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a fully isolated encapsulated plastic package using TrenchMOSTM technology.
FEATURES:
- Low on-state resistance
- Isolated package.
PHX8NQ11T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHX8NQ11T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a fully isolated encapsulated plastic package using TrenchMOSTM technology.
FEATURES:
- Low on-state resistance
- Isolated package.
PHP23NQ11T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHP23NQ11T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Low on-state resistance
- Low thermal resistance.
PHP/PHB174NQ04LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB174NQ04LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Very low on-state resistance.
PHP/PHB101NQ04T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB101NQ04T.html
DESCRIPTION:
N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Standard level threshold
- Very low on-state resistance.
PHP/PHB222NQ04LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB222NQ04LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Very low on-state resistance.
PHP27NQ11T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHP27NQ11T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Low on-state resistance
- Low thermal resistance.
PHP/PHB225NQ04T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB225NQ04T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Standard level threshold
- Very low on-state resistance.
PHX34NQ11T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHX34NQ11T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a fully isolated encapsulated plastic package using TrenchMOSTM technology.
FEATURES:
- Low on-state resistance
- Isolated package.
PHB95NQ04LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB95NQ04LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Low on-state resistance.
PHP34NQ11T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHP34NQ11T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Low on-state resistance
- Low thermal resistance.
PHX23NQ11T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHX23NQ11T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a fully isolated encapsulated plastic package using TrenchMOSTM technology.
FEATURES:
- Low on-state resistance
- Isolated package.
PHX27NQ11T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHX27NQ11T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a fully isolated encapsulated plastic package using TrenchMOSTM technology.
FEATURES:
- Low on-state resistance
- Isolated package.
PHP/PHB143NQ04T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB143NQ04T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Standard level threshold
- Very low on-state resistance.
PHP/PHB129NQ04LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB129NQ04LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Very low on-state resistance.
Logic
PCA24S08
1024 x 8-bit CMOS EEPROM with access protection
http://my.semiconductors.philips.com/pip/PCA24S08D.html
DESCRIPTION:
The PCA24S08 provides 8192 bits of serial electrically erasable and programmable Read-only memory (EEPROM) organized as 1024 words of 8 bits each. Data bytes are received and transmitted via the serial I2C-bus.
Access permissions limiting reads or writes are set via the I2C-bus to isolate blocks of memory from improper access.
The PCA24S08 is intended to be pin compatible with standard 24C08 serial EEPROM devices except for pins 1, 2, and 3, which are address pins in the standard part. Other exceptions to the PCA24C08 serial EEPROM datasheet are noted the ⌠Serial EEPROM Exception■ section later in this document.
All bits are sent to or read from the device, most significant bit first, in a manner consistent with the 24C08 serial EEPROM. The bit fields in this document are correspondingly listed with the MSB on the left and the LSB on the right.
The EEPROM memory is broken up into 8 blocks of 1 k bits (128 bytes) each. Within each block, the memory is physically organized in to 8 pages of 128 bits (16 bytes) each. In addition to these 8 k bits, there are two more 128-bit pages that are used to store the access protection and ID information. There are a total of 8448 bits of EEPROM memory available in the PCA24S08.
Access protection (both read and write) is organized on a block basis for blocks 1 through 7 and on a page and a block basis for block 0. Protection information for these blocks and pages is stored in one of the additional pages of EEPROM memory that is addressed separately from the main data storage array. See ⌠Access Protection■ for more details.
The ID value (see ⌠ID Configuration■) is located in the ID page of the EEPROM, the second of the additional 16 byte pages.
Writes from the serial interface may include from one to 16 bytes at a time, depending on the protocol followed by the bus master. All page accesses must be properly aligned to the internal EEPROM page.
The EEPROM memory offers an endurance of 100,000 write cycles per byte, with 10 year data retention. Writes to the EEPROM take less than 5 ms to complete.
After manufacturing, all EEPROM bits will be set to a value of ▒1▓.
FEATURES:
- Non-volatile storage of 8 kbits organized as 8 blocks of 128 bytes each
- I2C interface logic
- Compatible with 24C08 Serial EEPROM, and alternate source of Atmel AT24RF08C without the RF interface
- Write operation:
- Byte write mode
- 16-byte page write mode
- Read operation:
- Sequential read
- Random read
- Programmable access protection to limit reads and writes
- Lock/unlock function
- Write protect feature protecting the full memory array against write operations
- Self timed write cycle
- Internal power-on reset
- High reliability:
- Ten years non-volatile data retention time
- 100,000 write cycle endurance
- Low power CMOS technology
- Operating power supply voltage range of 2.5 V to 3.6 V
- 0 to 400 kHz clock frequency
- ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
- Packages offered: SO8, TSSOP8
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
http://my.semiconductors.philips.com/pip/74LVC3G14DC.html
DESCRIPTION:
The 74LVC3G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TLL-families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff . The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74LVC3G14 provides three inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
FEATURES:
- Wide supply voltage range from 1.65 V to 5.5 V
- 5 V tolerant input/output for interfacing with 5 V logic
- High noise immunity
- Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8-B/JESD36 (2.7 V to 3.6 V).
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- +-24 mA output drive (VCC = 3.0 V)
- CMOS low power consumption
- Latch-up performance exceeds 250 mA
- Direct interface with TLL levels
- SOT505-2 and SOT765-1 package
- Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel.
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
http://my.semiconductors.philips.com/pip/GTL1655DGG.html
DESCRIPTION:
The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive LOW-output-impedance (100 mA/12 Ohm) with LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL logic level translation.
The device is configured as two 8-bit transceivers that share a common clock and a master output enable pin, but also have individual latch timing and output enable signals. D-type flip-flops and D-type latches enable three modes of data transfer; Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The combination of reduced output swing, reduced input threshold levels and configurable edge control provides the higher speed operation of GTL/GTL+ backplanes.
The GTL1655 can be used at GTL (VTT = 1.2 V, VREF = 0.8 V) or GTL+ (VTT = 1.5 V, VREF = 1.0 V) signalling levels. Port A and the control inputs are compliant with LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or GTL+ signal levels, with VREF providing the reference voltage input.
The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA) and the clock pin (CP) are used to control the data flow through the two 8-bit transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be controlled. The OE pin can be used to disable all of the I/O pins.
To optimize signal integrity, the GTL1655 features an adjustable edge rate control (VERC ). By adjusting VERC between GND and VCC , a designer can adjust the Port B edge rate to suit an application▓s load conditions.
The GTL1655 permits true live insertion capability by incorporating:
- BIAS VCC , to pre-charge outputs and avoid disturbing active data during card insertion.
- Ioff to disable current flow through powered-off I/Os.
- Power-up 3-state, which ensures outputs are high-impedance during power-up, thus preventing bus contention issues. Once VCC is above 1.5 V, the power-up 3-state circuit relinquishes control of the outputs to the OE pin. To ensure the outputs remain 3-state, the OE pin should be tied to VCC via a pull-up resistor.
FEATURES:
- Combination of D-type latches and D-type flip-flops for transceiver operation in clocked, latched or transparent mode
- Logic level translation between LVTTL and GTL/GTL+ signals
- HIGH-drive LOW-output-impedance (100 mA/12 Ohm) on Port B
- Configurable rise and fall times on Port B
- Supports live insertion (Ioff, Power-up 3-state, and BIAS VCC)
- Bus Hold on Port A inputs
- Over voltage tolerance on Port A
- Minimized switching noise through use of distributed VCC and GND pins
- Available in TSSOP64 package
- Industrial temperature range (-40 Cel to +85Cel)
- ESD protection
- HBM EIA/JESD22-A114-A exceeds 2000 V
- CDM EIA/JESD22-C101 exceeds 1000 V
- Latch-up EIA/JEDS78 exceeds 200 mA
Updated product information
Logic
GTL2005 (UPDATED)
Quad GTL-/GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
http://my.semiconductors.philips.com/pip/GTL2005PW.html
DESCRIPTION:
The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL√/GTL/GTL+ bus.
The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface.
The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL on 5 V CMOS outputs.
FEATURES:
- Operates as a quad GTL√/GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL√/GTL/GTL+ driver
- Quad bidirectional bus interface
- 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O
- Live insertion/extraction permitted
- Latch-up protection exceeds 500 mA per JESD78
- ESD protection exceeds 2000 V HBM per JESD22-A114 200 V mm per JESD22-A115, and 1000 V CDM per JESD22-CC101
- Package offered: TSSOP14
74LVC823A (UPDATED)
9-bit D-type flip-flop with 5 V tolerant inputs/outputs;
positive edge-trigger; 3-state
http://my.semiconductors.philips.com/pip/74LVC823AD.html
DESCRIPTION:
The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
FEATURES:
- 5 V tolerant inputs/outputs for interfacing with 5 V logic
- Wide supply voltage range from 1.2 V to 3.6 V
- Inputs accept voltages up to 5.5 V
- CMOS low power consumption
- Direct interface with TTL levels
- Flow-through pin-out architecture
- 9-bit positive edge-triggered register
- Independent register and 3-state buffer operation
- Complies with JEDEC standard JESD8-B/JESD36
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- Specified from 40 Cel to +85 Cel and -40 Cel to +125 Cel.
PCA9504A (UPDATED)
Glue chip 4
http://my.semiconductors.philips.com/pip/PCA9504ADGG.html
DESCRIPTION:
The PCA9504A Glue Chip 4 is a highly integrated and cost-efficient custom ASIC that reduces logic part count, overall component cost, and board space requirements for PC designers and manufacturers. The Glue Chip 4 supports the latest generation of high-volume platforms based on Intel[ processors and chipsets that require additional external circuitry in order to function properly. It is used on entry servers/workstations (840 and 860 chipsets), high-end desktops (820 and 850 chipsets), as well as mid range (815, 830 and 845 chipsets) and low-end (810 chipset) motherboards. Some of these functionalities include meeting timing specifications, buffering signals, and switching between power wells.
The PCA9504A Glue Chip 4 integrates miscellaneous motherboard logic and analog functions into a single, small footprint 56-pin TSSOP device. The Glue Chip 4 typically resides on the motherboard close to the I/O controller Hub (ICH) and is optimized for the Intel 82801BA I/O controller hub (ICH2).
FEATURES:
- Dual, Strapping, Selectable Feature Sets
- Audio-disable Circuit
- Mute Audio Circuit
- 5 V reference generation
- 5 V standby reference generation
- HD single color LED driver
- IDE reset signal generation/PCIRST# buffers
- PWROK (PWRGD_3V) signal generation
- Power Sequencing / BACKFEED_CUT
- Power Supply turn on circuitry
- RMSRST# generation
- Voltage translation for DDC to VGA monitor
- HSYNCH / VSYNCH voltage translation to VGA monitor
- 3-state buffers for test
- Extra GP Logic gates
- Power LED Drivers
- Flash FLUSH# / INIT# circuit
- 5 V I2C to 3.3 V SMBus conversion to 400 kHz
- Requires both 3.3 V and 5.0 V operating voltages
- 0 to +70 Cel operating temperature range
- ESD protection exceeds 1000 V HBM per JESD22-A114 and 750 V
CDM per JESD22-C101
- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
- Package offered: TSSOP56 |
| |
| 17/05/2004 |
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eNews from Philips Semiconductors
Product of the week
LPC2194
Single-chip 32-bit micro with CAN
http://www.semiconductors.philips.com/pip/LPC2194JBD64.html
Featuring 4 CAN channels and a 10-bit ADC, the LPC2194 is a highly integrated ARM7-based microcontroller operating at up to 60 MHz. With its extensive array of interfaces and 256 Kbytes of high-performance embedded Flash, it is perfect for a host of applications including communications gateways, protocol converters and automotive networking.
Top headlines
- Philips strengthens comprehensive multimedia portfolio with Symbian partnership
http://www.semiconductors.philips.com/news/content/file_1060.html
- Philips announces LifePix: Algorithms for enhanced image quality on mobile displays
http://www.semiconductors.philips.com/news/content/file_1059.html
- Philips proves first silicon from 90-nm CMOS production line
http://www.semiconductors.philips.com/news/content/file_1058.html
News articles
╣TrenchMOS - a new dimension in power
With the release of a new series of highly efficient MOSFETs in the ultra-compact SOT416 (SC-75) package, Philips provides even more power management options for system designers. Part of the ╣TrenchMOS family, the new PMR devices boast extremely low RDS(on) values and are available in 20 V, 30 V and 60 V options. For more details, download our product leaflet
http://www.semiconductors.philips.com/acrobat/literature/9397/75013081.pdf.
New STARplug SMPS controller ICs
The new TEA162x devices are highly efficient controller ICs that enable the creation of compact and environmentally friendly switched mode power supplies (SMPSs). They are manufactured using Philips' high-voltage EZ-HV silicon-on-insulator technology combined with a low-voltage BiCMOS process, and operate from a rectified universal mains supply. The first products in the family are:
- TEA1620P
http://www.semiconductors.philips.com/pip/TEA1620P_N1.html
- TEA1622P
http://www.semiconductors.philips.com/pip/TEA1622P_N1.html
- TEA1623P
http://www.semiconductors.philips.com/pip/TEA1623P_N1.html
New product information
Discretes: Power
PHP/PHB174NQ04LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB174NQ04LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Very low on-state resistance.
PHP/PHB101NQ04T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB101NQ04T.html
DESCRIPTION:
N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Standard level threshold
- Very low on-state resistance.
PHP/PHB222NQ04LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB222NQ04LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Very low on-state resistance.
PHP/PHB225NQ04T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB225NQ04T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Standard level threshold
- Very low on-state resistance.
PHX34NQ11T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHX34NQ11T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a fully isolated encapsulated plastic package using TrenchMOSTM technology.
FEATURES:
- Low on-state resistance
- Isolated package.
PHB95NQ04LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB95NQ04LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Low on-state resistance.
PHP/PHB176NQ04T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB176NQ04T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Standard level threshold
- Very low on-state resistance.
PHB146NQ06LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB146NQ06LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Low on-state resistance.
PHP/PHB143NQ04T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB143NQ04T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Standard level threshold
- Very low on-state resistance.
PHP/PHB129NQ04LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB129NQ04LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Very low on-state resistance.
Logic
PCA24S08
1024 x 8-bit CMOS EEPROM with access protection
http://my.semiconductors.philips.com/pip/PCA24S08D.html
DESCRIPTION:
The PCA24S08 provides 8192 bits of serial electrically erasable and programmable Read-only memory (EEPROM) organized as 1024 words of 8 bits each. Data bytes are received and transmitted via the serial I2C-bus.
Access permissions limiting reads or writes are set via the I2C-bus to isolate blocks of memory from improper access.
The PCA24S08 is intended to be pin compatible with standard 24C08 serial EEPROM devices except for pins 1, 2, and 3, which are address pins in the standard part. Other exceptions to the PCA24C08 serial EEPROM datasheet are noted the ⌠Serial EEPROM Exception■ section later in this document.
All bits are sent to or read from the device, most significant bit first, in a manner consistent with the 24C08 serial EEPROM. The bit fields in this document are correspondingly listed with the MSB on the left and the LSB on the right.
The EEPROM memory is broken up into 8 blocks of 1 k bits (128 bytes) each. Within each block, the memory is physically organized in to 8 pages of 128 bits (16 bytes) each. In addition to these 8 k bits, there are two more 128-bit pages that are used to store the access protection and ID information. There are a total of 8448 bits of EEPROM memory available in the PCA24S08.
Access protection (both read and write) is organized on a block basis for blocks 1 through 7 and on a page and a block basis for block 0. Protection information for these blocks and pages is stored in one of the additional pages of EEPROM memory that is addressed separately from the main data storage array. See ⌠Access Protection■ for more details.
The ID value (see ⌠ID Configuration■) is located in the ID page of the EEPROM, the second of the additional 16 byte pages.
Writes from the serial interface may include from one to 16 bytes at a time, depending on the protocol followed by the bus master. All page accesses must be properly aligned to the internal EEPROM page.
The EEPROM memory offers an endurance of 100,000 write cycles per byte, with 10 year data retention. Writes to the EEPROM take less than 5 ms to complete.
After manufacturing, all EEPROM bits will be set to a value of
▒1▓.
FEATURES:
- Non-volatile storage of 8 kbits organized as 8 blocks of 128 bytes each
- I2C interface logic
- Compatible with 24C08 Serial EEPROM, and alternate source of Atmel AT24RF08C without the RF interface
- Write operation:
- Byte write mode
- 16-byte page write mode
- Read operation:
- Sequential read
- Random read
- Programmable access protection to limit reads and writes
- Lock/unlock function
- Write protect feature protecting the full memory array against write operations
- Self timed write cycle
- Internal power-on reset
- High reliability:
- Ten years non-volatile data retention time
- 100,000 write cycle endurance
- Low power CMOS technology
- Operating power supply voltage range of 2.5 V to 3.6 V
- 0 to 400 kHz clock frequency
- ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
- Packages offered: SO8, TSSOP8
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
http://my.semiconductors.philips.com/pip/74LVC3G14DC.html
DESCRIPTION:
The 74LVC3G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TLL-families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff . The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74LVC3G14 provides three inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
FEATURES:
- Wide supply voltage range from 1.65 V to 5.5 V
- 5 V tolerant input/output for interfacing with 5 V logic
- High noise immunity
- Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8-B/JESD36 (2.7 V to 3.6 V).
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- +-24 mA output drive (VCC = 3.0 V)
- CMOS low power consumption
- Latch-up performance exceeds 250 mA
- Direct interface with TLL levels
- SOT505-2 and SOT765-1 package
- Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel.
GTL1655
16-bit LVTTL-to-GTL/GTL+ bus transceiver with live insertion
http://my.semiconductors.philips.com/pip/GTL1655DGG.html
DESCRIPTION:
The GTL1655 is a 16-bit bus transceiver that incorporates HIGH-drive LOW-output-impedance (100 mA/12 Ohm) with LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL logic level translation.
The device is configured as two 8-bit transceivers that share a common clock and a master output enable pin, but also have individual latch timing and output enable signals. D-type flip-flops and D-type latches enable three modes of data transfer; Clocked, Latched, or Transparent. The GTL1655 provides the ideal interface between cards operating at LVTTL levels and backplanes using GTL/GTL+ signal levels. The combination of reduced output swing, reduced input threshold levels and configurable edge control provides the higher speed operation of GTL/GTL+ backplanes.
The GTL1655 can be used at GTL (VTT = 1.2 V, VREF = 0.8 V) or GTL+ (VTT = 1.5 V, VREF = 1.0 V) signalling levels. Port A and the control inputs are compliant with LVTTL signal levels and are 5 V tolerant. Port B is designed to operate at GTL or GTL+ signal levels, with VREF providing the reference voltage input.
The latch enable pins (nLEAB and nLEBA), the output enable pins (nOEAB, nOEBA) and the clock pin (CP) are used to control the data flow through the two 8-bit transceivers (n = 1 or 2). When nLEAB is set HIGH, the device will operate in the transparent mode Port A to Port B. HIGH-to-LOW transitions of nLEAB will latch A data independently of CP HIGH or LOW (latched mode). LOW-to-HIGH transitions of CP will clock A data to the B port if nLEAB is LOW (clocked mode). Using the control pins nLEBA, nOEBA and CP in the same way, data flow from Port B to Port A can be controlled. The OE pin can be used to disable all of the I/O pins.
To optimize signal integrity, the GTL1655 features an adjustable edge rate control (VERC ). By adjusting VERC between GND and VCC , a designer can adjust the Port B edge rate to suit an application▓s load conditions.
The GTL1655 permits true live insertion capability by incorporating:
- BIAS VCC , to pre-charge outputs and avoid disturbing active data during card insertion.
- Ioff to disable current flow through powered-off I/Os.
- Power-up 3-state, which ensures outputs are high-impedance
during power-up, thus preventing bus contention issues. Once VCC is above 1.5 V, the power-up 3-state circuit relinquishes control of the outputs to the OE pin. To ensure the outputs remain 3-state, the OE pin should be tied to VCC via a pull-up resistor.
FEATURES:
- Combination of D-type latches and D-type flip-flops for transceiver operation in clocked, latched or transparent mode
- Logic level translation between LVTTL and GTL/GTL+ signals
- HIGH-drive LOW-output-impedance (100 mA/12 Ohm) on Port B
- Configurable rise and fall times on Port B
- Supports live insertion (Ioff, Power-up 3-state, and BIAS VCC)
- Bus Hold on Port A inputs
- Over voltage tolerance on Port A
- Minimized switching noise through use of distributed VCC and GND pins
- Available in TSSOP64 package
- Industrial temperature range (-40 Cel to +85Cel)
- ESD protection
- HBM EIA/JESD22-A114-A exceeds 2000 V
- CDM EIA/JESD22-C101 exceeds 1000 V
- Latch-up EIA/JEDS78 exceeds 200 mA
Updated product information
Logic
74LVC623A (UPDATED)
Octal transceiver with dual enable; 3-state
http://my.semiconductors.philips.com/pip/74LVC623AD.html
DESCRIPTION:
The 74LVC623A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V or 5 V environment.
The 74LVC623A is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. This octal bus transceiver is designed for asynchronous two-way communication between data buses.
The control function implementation allows maximum flexibility in timing. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the enable inputs (pins OEAB and OEBA). The enable inputs can be used to disable the device so that the buses are effectively isolated. The dual enable function configuration gives this transceiver the capability to store data by simultaneous enabling of pins OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of the bus lines are at high-impedance OFF-state, both sets of the bus lines will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical.
FEATURES:
- 5 V tolerant inputs and outputs for interfacing with 5 V logic
- Wide supply voltage range from 1.2 V to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- Inputs accept voltages up to 5.5 V
- High-impedance when VCC =0 V
- Complies with JEDEC standard JESD8-B/JESD36
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- Specified from -40 Cel to +85Cel and from -40 Cel to +125 Cel.
GTL2005 (UPDATED)
Quad GTL-/GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
http://my.semiconductors.philips.com/pip/GTL2005PW.html
DESCRIPTION:
The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL√/GTL/GTL+ bus.
The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface.
The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL on 5 V CMOS outputs.
FEATURES:
- Operates as a quad GTL√/GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL√/GTL/GTL+ driver
- Quad bidirectional bus interface
- 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O
- Live insertion/extraction permitted
- Latch-up protection exceeds 500 mA per JESD78
- ESD protection exceeds 2000 V HBM per JESD22-A114 200 V mm per JESD22-A115, and 1000 V CDM per JESD22-CC101
- Package offered: TSSOP14
74LVCH322245A (UPDATED)
32-bit bus transceiver with direction pin; 30 Ohm series termination resistors; 5 V tolerant; 3-state
http://my.semiconductors.philips.com/pip/74LVCH322245AEC.html
DESCRIPTION:
The 74LVCH322245A is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.
The 74LVCH322245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The 74LVCH322245A features four output enable inputs (nOE) for easy cascading and four send or receive inputs (nDIR) for direction control. Pin nOE controls the outputs, so that the buses are effectively isolated. The 74LVCH322245A is designed with 30 Ohm series termination resistors in both HIGH and LOW output stages to reduce line noise.
To ensure the high-impedance state during power up or power down, pin nOE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The 74LVCH322245A bushold data input eliminates the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level.
FEATURES:
- 5 V tolerant inputs/outputs for interfacing with 5 V logic
- Wide supply voltage range of 1.2 V to 3.6 V
- CMOS low-power consumption
- MULTIBYTE flow-trough standard pin-out architecture
- Low inductance multiple power and ground pins for minimum noise and ground bounce
- Direct interface with TTL levels
- Inputs accept voltages up to 5.5 V
- All data inputs have bushold
- Integrated 30 Ohm termination resistors
- Complies with JEDEC standard JESD8-B/JESD36
- ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
- Specified from -40 Cel to +85 Cel
- Packaged in plastic fine-pitch ball grid array package.
74LVC823A (UPDATED)
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state
http://my.semiconductors.philips.com/pip/74LVC823AD.html
DESCRIPTION:
The 74LVC823A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
FEATURES:
- 5 V tolerant inputs/outputs for interfacing with 5 V logic
- Wide supply voltage range from 1.2 V to 3.6 V
- Inputs accept voltages up to 5.5 V
- CMOS low power consumption
- Direct interface with TTL levels
- Flow-through pin-out architecture
- 9-bit positive edge-triggered register
- Independent register and 3-state buffer operation
- Complies with JEDEC standard JESD8-B/JESD36
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- Specified from 40 Cel to +85 Cel and -40 Cel to +125 Cel.
PCA9504A (UPDATED)
Glue chip 4
http://my.semiconductors.philips.com/pip/PCA9504ADGG.html
DESCRIPTION:
The PCA9504A Glue Chip 4 is a highly integrated and cost-efficient custom ASIC that reduces logic part count, overall component cost, and board space requirements for PC designers and manufacturers. The Glue Chip 4 supports the latest generation of high-volume platforms based on Intel[ processors and chipsets that require additional external circuitry in order to function properly. It is used on entry servers/workstations (840 and 860 chipsets), high-end desktops (820 and 850 chipsets), as well as mid range (815, 830 and 845 chipsets) and low-end (810 chipset) motherboards. Some of these functionalities include meeting timing specifications, buffering signals, and switching between power wells.
The PCA9504A Glue Chip 4 integrates miscellaneous motherboard logic and analog functions into a single, small footprint 56-pin TSSOP device. The Glue Chip 4 typically resides on the motherboard close to the I/O controller Hub (ICH) and is optimized for the Intel 82801BA I/O controller hub (ICH2).
FEATURES:
- Dual, Strapping, Selectable Feature Sets
- Audio-disable Circuit
- Mute Audio Circuit
- 5 V reference generation
- 5 V standby reference generation
- HD single color LED driver
- IDE reset signal generation/PCIRST# buffers
- PWROK (PWRGD_3V) signal generation
- Power Sequencing / BACKFEED_CUT
- Power Supply turn on circuitry
- RMSRST# generation
- Voltage translation for DDC to VGA monitor
- HSYNCH / VSYNCH voltage translation to VGA monitor
- 3-state buffers for test
- Extra GP Logic gates
- Power LED Drivers
- Flash FLUSH# / INIT# circuit
- 5 V I2C to 3.3 V SMBus conversion to 400 kHz
- Requires both 3.3 V and 5.0 V operating voltages
- 0 to +70 Cel operating temperature range
- ESD protection exceeds 1000 V HBM per JESD22-A114 and 750 V
CDM per JESD22-C101
- Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
- Package offered: TSSOP56 |
| |
| 10/05/2004 |
|
eNews from Philips Semiconductors
Product of the week
BGA2715
Generic 50 Ohm gain block
http://www.semiconductors.philips.com/pip/BGA2715.html
One of a range of Monolithic Microwave ICs (MMICs), the BGA2715 general-purpose gain block offers high gain, low noise, good linearity and unconditional stability. It is ideal for LNB IF amplifiers, ISM and cable systems.
News articles
New PCA9564 I2C bus controller evaluation board
To let customers see capabilities of the new PCA9564 I2C bus controller for themselves, Philips offers a microcontroller-based evaluation board http://www.philipslogic.com/support/boards/pca9564/.
The board demonstrates the controller ability to interface between any I2C master or slave device and microcontroller or microprocessor that does not have an I2C port. The board is available free of charge, while software and a user manual can be downloaded from the Internet. To request the kit, send an e-mail including shipping address, point of contact, phone number, application and volume potential to I2C.Support@philips.com mailto:I2C.Support@philips.com.
New product information
Discretes: Power
PHP/PHB119NQ06T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB119NQ06T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Standard level threshold
- Very low on-state resistance.
PHP/PHB110NQ06LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB110NQ06LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOTM technology.
FEATURES:
-Logic level threshold
-Low on-state resistance.
PHP/PHB191NQ06LT
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PHB191NQ06LT.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Logic level threshold
- Very low on-state resistance.
PHB145NQ06T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB145NQ06T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSЎЭ technology.
FEATURES:
- Standard level threshold
- Low on-state resistance.
PHP/PHB193NQ06T
N-channel Trenchmos (tm) standard level FET
http://my.semiconductors.philips.com/pip/PHB193NQ06T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSЎЭ technology.
FEATURES:
- Standard level threshold
- Very low on-state resistance.
Logic
74LVC3G04
Triple inverter
http://my.semiconductors.philips.com/pip/74LVC3G04DC.html
DESCRIPTION:
The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff . The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74LVC3G04 provides three inverting buffers.
FEATURES:
- Wide supply voltage range from 1.65 V to 5.5 V
- 5 V tolerant outputs for interfacing with 5 V logic
- High noise immunity
- Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8-B/JESD36 (2.7 V to 3.6 V).
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- +-24 mA output drive (VCC = 3.0 V)
- CMOS low power consumption
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- SOT505-2 and SOT765-1 package
- Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel.
74LVC3G34
Triple buffer gate
http://my.semiconductors.philips.com/pip/74LVC3G34DC.html
DESCRIPTION:
The 74LVC3G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff . The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74LVC3G34 provides three buffers.
FEATURES:
- Wide supply voltage range from 1.65 V to 5.5 V
- 5 V tolerant input/output for interfacing with 5 V logic
- High noise immunity
- Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8-B/JESD36 (2.7 V to 3.6 V).
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- +-24 mA output drive (VCC = 3.0 V)
- CMOS low power consumption
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- SOT505-2 and SOT765-1 package
- Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel.
Updated product information
Logic
74LV132 (UPDATED)
Quad 2-input NAND Schmitt trigger
http://my.semiconductors.philips.com/pip/74LV132D.html
DESCRIPTION:
The 74LV132 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC132 and 74HCT132.
The 74LV132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the hysteresis voltage VH .
FEATURES:
- Wide operating voltage: 1.0 V to 5.5 V
- Optimized for low voltage applications: 1.0 V to 3.6 V
- Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
- Typical output ground bounce VOLP < 0.8 V at VCC = 3.3 V and
Tamb = 25 Cel
- Typical output VOH undershoot VOHV > 2 V at VCC = 3.3 V and
Tamb = 25 Cel
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- Specified from -40 Cel to +80Cel and from -40 Cel to +125 Cel.
74LVC821A (UPDATED) 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
http://my.semiconductors.philips.com/pip/74LVC821AD.html
DESCRIPTION:
The 74LVC821A is a high performance, low power, low voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.
The 74LVC821A is a 10-bit D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (pin CP) and an output enable input (pin OE) are common to all flip-flops. The ten flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the ten flip-flops is available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE inputs does not affect the state of the flip-flops.
FEATURES:
- 5 V tolerant inputs and outputs; for interfacing with 5 V
logic
- Wide supply voltage range from 1.2 V to 3.6 V
- Inputs accept voltages up to 5.5 V
- CMOS low power consumption
- Direct interface with TTL levels
- Flow-through pin-out architecture
- 10-bit positive edge-triggered register
- Independent register and 3-state buffer operation
- Complies with JEDEC standard JESD8-B
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel.
74LVC163 (UPDATED)
Presettable synchronous 4-bit binary counter; synchronous reset
http://my.semiconductors.philips.com/pip/74LVC163D.html
DESCRIPTION:
The 74LVC163 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.
The 74LVC163 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going transition on the clock input (pin CP) (provided that the set-up and hold time requirements for PE are met). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pins CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by tPHL (propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula: f max = 1/(tPHL(max) + tsu)
FEATURES:
- Wide supply voltage range from 1.2 V to 3.6 V
- Complies with JEDEC standard JESD8-B/JESD36
- Inputs accept voltages up to 5.5 V
- CMOS low power consumption
- Direct interface with TTL levels
- Synchronous reset
- Synchronous counting and loading
- Two count enable inputs for n-bit cascading
- Positive edge-triggered clock.
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel.
74LVC1G80 (UPDATED)
Single D-type flip-flop; positive-edge trigger
http://my.semiconductors.philips.com/pip/74LVC1G80GW.html
DESCRIPTION:
The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using Ioff . The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop.
Information on the data input is transferred to the Q output pin on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
FEATURES:
- Wide supply voltage range from 1.65 V to 5.5 V
- High noise immunity
- Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8B/JESD36 (2.7 V to 3.6 V).
- +-24 mA output drive (VCC = 3.0 V)
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- CMOS low power consumption
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- Inputs accept voltages up to 5 V
- Multiple package options
- Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel.
74AHC74; 74AHCT74 (UPDATED)
Dual D-type flip-flop with set and reset; positive-edge trigger
http://my.semiconductors.philips.com/pip/74AHCT74D.html
DESCRIPTION:
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.
The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
FEATURES:
- ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
- Balanced propagation delays
- Inputs accepts voltages higher than VCC
- For 74AHC74 only: operates with CMOS input levels
- For 74AHCT74 only: operates with TTL input levels
- Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel. |
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| 03/05/2004 |
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eNews from Philips Semiconductors
Product of the week
74ALVCxxx
Gates and octals in DQFN
http://www.philipslogic.com/products/alvc/new/
The very-high-speed, low-power ALVC logic family now includes a number of functions in the leadless DQFN package - the world's smallest package for gates and octal functions. Suitable for all low-voltage / low-power applications, particularly those requiring high performance, these recent releases offer space savings of around 70% over the previous best-in-class.
Top headlines
- Philips chip technology selected by the ERG Group to power Seattle land and ferry transit smart card system
http://www.semiconductors.philips.com/news/content/file_1057.html
New product information
Discretes: Power
PH2625L
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PH2625L.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Optimized for use in DC-to-DC converters
- Very low switching and conduction losses
- Low threshold voltage
- Low thermal resistance.
PH6325L
N-channel Trenchmos (tm) logic level FET
http://my.semiconductors.philips.com/pip/PH6325L.html
DESCRIPTION:
Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- Optimized for use in DC-to-DC converters
- Very low switching and conduction losses
- Low threshold voltage
- Low thermal resistance.
Updated product information
Discretes: Power
PHN103T (UPDATED)
N-channel enhancement mode field-effect transistor
http://my.semiconductors.philips.com/pip/PHN103T.html
DESCRIPTION:
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology.
FEATURES:
- TrenchMOSTM technology
- Fast switching
- Low on-state resistance
- Logic level compatible.
Discretes: RF
BB184 (UPDATED)
UHF Low Voltage variable capacitance diode
http://my.semiconductors.philips.com/pip/BB184.html
DESCRIPTION:
The BB184 is a variable capacitance diode, fabricated in planar technology, and encapsulated in the SOD523 (SC-79) ultra small SMD plastic package.
FEATURES:
- Very steep CV curve
- Cd(1V) : 14 pF; Cd(10V) : 2 pF
- Cd(1V) to Cd(10V) ratio: typical 7
- Ultra small SMD plastic package.
BB207 (UPDATED)
FM variable capacitance double diode
http://my.semiconductors.philips.com/pip/BB207.html
DESCRIPTION:
The BB207 is a variable capacitance double diode with a common cathode, fabricated in silicon planar technology, and encapsulated in the SOT23 small plastic SMD package.
FEATURES:
- Excellent linearity
- Cd(1V) : 81 pF; Cd(7.5V) : 27.6 pF
- Cd(1V) to Cd(7.5V) ratio: min. 2.6
- Very low series resistance
- Small plastic SMD package.
Logic
PCK210 (UPDATED)
Low voltage dual 1:5 differential ECL/PECL clock driver
http://my.semiconductors.philips.com/pip/PCK210BD.html
DESCRIPTION:
The PCK210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The input signals can be either differential or single-ended if the V BB output is used. The signal is fanned out to 5 identical differential outputs.
The PCK210 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tPD distributions from lot to lot. The net result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50 Ohm, even if only one side is being used. In most applications, all ten differential pairs will be used, and therefore terminated. In the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10ЎМ20 ps) of the output(s) being used, which, while not being catastrophic to most designs, will mean a loss of skew margin.
The PCK210, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the PCK210 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Designers can take advantage of the PCK210Ё€s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies.
The PCK210 may be driven single-endedly utilizing the VBB bias output with the CLKA or CLKB input. If a single-ended signal is to be used, the VBB pin should be connected to the CLKA or CLKB input and bypassed to ground via a 0.01 uF capacitor. The VBB output can only source/sink 0.3 mA, therefore, it should be used as a switching reference for the PCK210 only. Part-to-part skew specifications are not guaranteed when driving the PCK210 single-endedly.
FEATURES:
- 85 ps part-to-part skew typical
- 20 ps output-to-output skew typical
- Differential design
- VBB output
- Voltage and temperature compensated outputs
- Low voltage VEE range of ЎМ2.25 V to ЎМ3.8 V
- 75 kOhm input pull-down resistors
- Form, fit, and function compatible with MC100EP210
PCK111 (UPDATED)
Low voltage dual 1:10 differential ECL/PECL/HSTL clock driver
http://my.semiconductors.philips.com/pip/PCK111BD.html
DESCRIPTION:
The PCK111 is a low skew 1-to-10 differential driver, designed with clock distribution in mind. It accepts two clock sources into an input multiplexer. The PECL input signals can be either differential or single-ended if the VBB output is used. The selected signal is fanned out to 10 identical differential outputs.
The PCK111 is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tPD distributions from lot to lot. The net result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary that both sides of the differential output are terminated into 50 Ohm, even if only one side is being used. In most applications, all ten differential pairs will be used, and therefore terminated. In the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10ЎМ20 ps) of the output(s) being used, which, while not being catastrophic to most designs, will mean a loss of skew margin.
The PCK111 can be used for high performance clock distribution in +3.3 V or +2.5 V systems. Designers can take advantage of the PCK111Ё€s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies.
The PCK111 may be driven single-endedly utilizing the VBB bias output with the CLK0 input. If a single-ended signal is to be used, the VBB pin should be connected to the CLK0 input and bypassed to ground via a 0.01 uF capacitor. The VBB output can only source/sink 0.2 mA, therefore, it should be used as a switching reference for the PCK111 only. Part-to-part skew specifications are not guaranteed when driving the PCK111 single-endedly.
FEATURES:
- 85 ps part-to-part skew typical
- 20 ps output-to-output skew typical
- Differential design
- VBB output
- Low voltage VEE range of ЎМ2.25 V to ЎМ3.8 V for ECL
- Low voltage VCC range of +2.375 V to +3.8 V for PECL
- 75 kOhm input pull-down resistors
- ECL/PECL outputs
- Form, fit, and function compatible with MC100EP111 |
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